make

The Makefile for a one-binary C project, explained piece by piece. CC = gcc CFLAGS = -std=gnu23 -Og -g3 -Wall -Werror -Wextra -Wwrite-strings OUT = out BIN = $(OUT)/tinybox all: $(BIN) # Any out/<name> from <name>.c, e.g. `make out/scratch` $(OUT)/%: %.c Makefile | $(OUT) $(CC) $(CFLAGS) -o $@ $< $(OUT): mkdir -p $@ tinybox: $(BIN) scratch: $(OUT)/scratch run: $(BIN) ./$(BIN) clean: rm -rf $(OUT) .PHONY: all run clean tinybox scratch Rules target: prerequisites recipe make rebuilds target if it doesn’t exist or any prerequisite is newer (by file modification time). That’s the whole algorithm. The recipe lines must start with a tab. Spaces give *** missing separator. Stop. A rule with no recipe (tinybox: $(BIN)) just says “to make this, make that”. Variables CC, CFLAGS are conventional names (make’s built-in rules use them too). Use with $(NAME). Override from the command line: make CFLAGS=-O2. ...